The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a metal silicide layer.
Recently, demands for high capacity, high density integration, and high performance of semiconductor devices have been rapidly increasing. However, an increase in the degree of integration of semiconductor devices causes a need for a greater reduction in the line width of a pattern. As a result, source/drain regions and a gate electrode of a n-type MOS transistor or p-type MOS transistor exhibit a gradual decrease in width. For this reason, the surface resistance of the source/drain regions and gate electrode increases, and therefore, becomes the main reason of deterioration in the operational characteristics of devices. Accordingly, in order to restrict such an increase of the surface resistance, metal silicide layers have been placed on a surface of the source/drain regions and gate electrode.
Among a variety of metal silicide layers, in particular, a cobalt silicide (CoSi2) layer has a relatively low specific resistance of approximately 16 to 18 μΩ·cm. The cobalt silicide layer is also stable even at a high temperature of more than 800° C., and therefore, can reduce a thermal budget caused by a high-temperature reflow process for a following interlayer dielectric layer, for example, phosphorus silicate glass (PSG) layer or boron phosphorus silicate glass (BPSG) layer. The cobalt silicide layer has a low reactivity with a silicon oxide layer, and therefore, has a low possibility for causing deterioration in the characteristics of a device due to a side reaction. Another advantage of the cobalt silicide layer is in that it can maintain a constant contact resistance regardless of the kind of a device by virtue of a low dopant dependency thereof. Moreover, the cobalt silicide layer, which is composed of cobalt (Co) and a main diffuser, is horizontally formed. This has the effect of restricting the generation of a short between a source and a drain, and eliminating most of the damage with respect to a plasma etching process. Therefore, the cobalt silicide layer (CoSi2) has substantially no risk of damage even if excessive etching is performed to form bit line contact holes.
However, in spite of the above described many advantages, the cobalt silicide layer suffers from the following problems when it is applied to a semiconductor device, more particularly, a semiconductor memory device, such as a dynamic random access memory (DRAM). For example, when a self-align contact (SAC) etching process is performed to expose the surface of a substrate in a peripheral region, a gate spacer layer is previously formed around a sidewall of a gate stack by use of a nitride layer, in order to protect a gate conductive layer. However, when the self-align contact etching process is performed to open the peripheral region for the formation of the cobalt silicide layer (CoSi2), the gate spacer layer may be attacked. In a worse case, the gate spacer layer may be removed, and thus, a self-align contact failure may occur. This causes a problem of device malfunction. Additionally, the etching process may cause a loss of a silicon substrate, and simultaneously, a loss of dopant in source/drain regions, thereby making it impossible to achieve uniform characteristic distribution of transistors throughout a wafer.